In a known way, and as illustrated schematically in FIG. 1, a non-volatile memory device, designated by 1, for example of a NAND or NOR flash type, in general comprises a memory array 2 made up of a plurality of memory cells 3, arranged in rows (wordlines WL) and columns (data lines, or bitlines BL).
Each memory cell 3 is constituted by a storage element formed by a floating-gate transistor, with its gate terminal designed to be coupled to a respective wordline WL, a first conduction terminal designed to be coupled to a respective bitline BL, and a second conduction terminal connected to a reference potential (for example, to ground, GND). In particular, the gate terminals of the memory cells 3 of a same wordline WL are connected together.
In a way not illustrated, the memory array 2 is generally arranged in a plurality of sectors, each of which comprises a plurality of memory cells 3. Each sector has a plurality of respective wordlines WL, distinct from those of the other sectors and physically connected to the memory cells 3 present in the same sector.
A column decoder 4 and a row decoder 5 enable selection, on the basis of address signals received at an input (generated in a per se known manner and denoted in general by AS, ASr for the rows and ASc for the columns), of the memory cells 3, and in particular of the corresponding wordlines WL and bitlines BL, each time addressed in the various sectors, enabling biasing thereof at appropriate voltage and current values during memory operations.
The column decoder 4 may further be configured to provide internally two paths to the bitlines BL of the memory array 2 each time selected. A reading path is designed to define a conductive path between the selected bitline BL and a sense-amplifier stage 7, which designed to compare the current circulating in the addressed memory cell 3 with a reference current in order to determine the datum stored. A programming path is designed to define a conductive path between the selected bitline BL and a driving stage 8, configured to supply required biasing quantities.
In the specific case of the non-volatile memories of a flash type, it is known that memory operations require high values of the biasing voltage applied to the wordlines WL, for example a high voltage of 4.5 V, during the reading operations. These values of the biasing voltages are generated within the memory device by charge-pump stages, which generate a boosted voltage starting from a supply voltage Vdd, having a logic value, for example corresponding to a low voltage of 1.2 V.
The row decoder 5 thus usually has a configuration having a low-voltage portion and a high-voltage portion, which is to be coupled to the wordlines WL of the memory array 2 for supplying the required biasing quantities. Level shifters are used for shifting the low-voltage signals (for example, at 1.2 V) of the first portion of the row decoder 5 into high-voltage signals (for example, at 4.5 V) of the second portion of the same row decoder 5.
As illustrated schematically in FIG. 2, in a known embodiment, the row decoder 5 comprises an input module 10, which receives the row-address signals ASr, which are digital signals having a certain number of bits, from an input-address bus 11, and appropriately groups the bits of the same row-address signals ASr into subsets in order to generate low-voltage (LV) grouped address signals PASLV.
The row decoder 5 further comprises a pre-decoding module 12, which receives the grouped address signals PASLV and combines them logically in an appropriate way, generating pre-decoded address signals PASLV, which are also at low voltage, on a first transport bus 13, which includes a certain number of lines, corresponding to each of which is a respective combination of the grouped address signals PASLV.
Through the aforesaid first transport bus 13, the pre-decoded address signals PASLV then reach a voltage-booster module 14, which receives at an input the same pre-decoded address signals PASLV and generates high-voltage (HV) pre-decoded address signals PASHV on a second transport bus 15, which includes a number of lines corresponding to the number of lines of the first transport bus 13.
The row decoder 5 further comprises a decoding module 16, which receives the high-voltage pre-decoded address signals PASHV and combines them logically in an appropriate way to generate high-voltage decoded address signals DASHV on an output bus 17, which includes a number of lines corresponding to the number of wordlines WL of the addressed sector of the memory array 2. The row decoder 5 also comprises a driving module 18, which receives the decoded address signals DASHV from the output bus 17 and generates appropriate high-voltage biasing signals S_WL for the respective wordlines WL of the sector of the memory array 2 in such a way as to enable addressing and biasing of the corresponding memory cells 3.
In particular, in the row decoder 5 the low-voltage portion thus includes the input module 10 and the pre-decoding module 12 (which thus operate in the low-voltage range, i.e., with voltages in the region of the supply voltage Vdd, for example 1.2 V), whereas the high-voltage portion, separated from the aforesaid low-voltage portion by the voltage-booster module 14, includes the decoding module 16 and the driving module 18 (which thus operate in the high-voltage range, i.e., with voltages in the region of the boosted voltage, for example 4.5 V).
Architectures of row decoders 5 built in a way substantially similar to what has been described are illustrated, for example, in:
P. Cappelletti, C. Golla, P. Olivo, E. Zanoni, “Flash Memories”, Kluver Academic Publishers, 1999, Chapter 5.2;
G. Campardo, “Progettazione di memorie non-volatili”, Franco Angeli 2002, p. 199-205.